Senior VLSI Verification Engineer
חברה מובילה בשוק רעננה
Senior
דרישות חובה
VLSIUVMSystemVerilog
יתרון
SoCASICVerification (DV)Python
תיאור המשרה
A fast‑growing semiconductor startup is looking for a talented Senior VLSI Verification Engineer to take full ownership of block‑level and subsystem‑level verification. If you love building verification environments from scratch, thrive in lean teams, and want real impact - this one’s for you! What you’ll do: • Own the full verification lifecycle • Build advanced UVM/SystemVerilog environments • Drive SVA‑based verification and deep debug • Develop constrained‑random & directed tests • Automate flows using Python + Linux • Collaborate closely with RTL designers & architects Big plus: • SoC‑level verification experience • Familiarity with embedded CPUs (RISC‑V / ARM) & AXI/AHB/APB